Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing, blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Although the following description is in terms of FPGAs, it should be understood that other Application Specific Standard Products (“ASSPs”), as well as Application Specific Integrated Circuits (“ASICs”), may be used for wireless communication functions. Furthermore, it should be appreciated that FPGAS, as well as other ASSPs, and ASICs may have discretely sized memory blocks.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Multiple-input, multiple-output orthogonal frequency division multiplexing (“MIMO-OFDM”) systems are gaining popularity. For example, MIMO-OFDM systems are making their way into more recent wireless communication standards such as IEEE 802.11n, 802.16, and 802.16e, among other known or proposed standards. Many of these MIMO-OFDM systems involve varying Fourier transform sizes, data rates, antenna configurations, and MIMO modulation schemes. Examples of MIMO modulation schemes include Space-Time Block Code (“STBC”) and spatial multiplexing, among other known MIMO modulation schemes.
Heretofore, an STBC encoder for a two-antenna transmitter system encoded two streams of symbols over two time intervals and stored the two streams of symbols over such two time intervals modifying such symbols in each time interval, namely a block length of two. This meant that for a MIMO-OFDM modulator, all samples of the OFDM symbol for each antenna were stored over multiple OFDM symbol intervals. For example, for a three-antenna transmitter system, the STBC block length is four and thus the samples are stored for four symbol intervals. Furthermore, for a four-antenna transmitter system, the block length increases to eight symbol intervals. Thus, conventionally, there may be a one-to-one correspondence of OFDM blocks with antennas. Furthermore, there may be a one-to-one correspondence between memory and antennas for an STBC encoder. In any of these instances, the amount of circuitry significantly increases as the number of antennas increase. Furthermore, if the memory is provided in discrete sizes significantly larger than the amount of buffer space used for each antenna, a significant amount of storage goes unused. Thus, as the number of antennas increases, not only do the circuit resources increase but also the amount of unused or wasted circuit resources associated with memory utilization may also increase.
Accordingly, it would be desirable to provide a MIMO-OFDM modulator that is efficient in data storage to effectively reduce the amount of unused or wasted memory resources.